A semiconductor package includes a semiconductor element, a package substrate, and a wiring substrate (interposer), which electrically connects the semiconductor element and the package substrate (e.g., Japanese Laid-Open Patent Publication No. 2002-190543, Japanese Laid-Open Patent Publication No. 2004-342988, WO 2003/030602). The interposer has one surface (e.g., upper surface) including bumps that are connected to the semiconductor element and another surface (e.g., lower surface) including bumps that are connected to the package substrate. The interposer includes wiring layers that electrically connect the bumps formed on the two surfaces to each other.
The pitch of connection terminals (pads) for a semiconductor element, such as a memory, has become narrow. When increasing the number of wiring layers in the interposer to cope with the narrow connection terminal pitch, the thickness of the interposer increases. This may enlarge the semiconductor package.